excamera, what I'm hacking on, daily.

jamesb@excamera.com

Board time
OK, the experiment seems to have been a success. I suspect some of its problems are caused by the very long traces (6") between the FPGA and the RTL8019. (I get TCP checksum errors unless I insert extra NOPs in the I/O subroutines).

It's time to design a board. Olimex always gives you 160 mm x 100 mm, so a 79x49 board gets you 4. What to make? Well, I plan to re-do something I made last year. It's a TCP/IP -> S/PDIF converter: it just sits on the network and forwards a byte stream to a digital audio interface. So a simple process on a server can decode MP3s, OGGs or whatever and forward it to the tiny device.

The one I made last year uses a Rabbit module for TCP/IP and the necessarily large FIFO. It also has an FPGA to drive the S/PDIF TOSLINK interface. It worked OK - it's still running - but skips about once every 10 minutes, can't do more than 44.1kHz at 16bit, sometimes just dies, and because of the $55 Rabbit module, cost me about $80 in parts. The biggest headache was that the TCP/IP stack couldn't handle the sustained bandwidth: 1.41Mbit/s. I had to do a bunch of weird hacks to get it to accept packets fast enough.

So this time will be different. Parts:

• For the FPGA, the Xilinx XC2S30. This is the CPU and controller.
• For Ethernet, RTL8019AS connected with a 16-bit interface
• Buffering for 2 seconds of audio: a cheap 4 mbit DRAM
• Bootstrap the FPGA with a cheap PIC and serial EEPROM

This should be able to handle 48KHz at 24 bit. For MP3 decoding, MAD produces 24 bit output.

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DRAM
Jameco has a cheap ($3) 256kx16 70ns DRAM, part number 128688CP. It's the same as this DRAM from Micron.

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