changequote([, ])

include(vhdlcommon.inc)

define(binary, ["eval($1, 2, $2)"])

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;

define(VERSION, TCPIP)

entity c2a is
    port (clock_in : in std_logic;

          hostIN : in  std_logic;
          hostOUT: out  std_logic;
          hostSTA  : in std_logic;
          hostCLK_g : in std_logic;

          ntsc300 : out std_logic;
          ntsc600 : out std_logic;

          ramDQ : inout std_logic_vector(32 downto 1);
          ramA : out std_logic_vector(11 downto 0);
          ramCAS : out std_logic_vector(3 downto 0);
          ramRAS : out std_logic_vector(3 downto 0);
          ramWE : out std_logic;

ifelse(VERSION, TCPIP, [
          ccdD_01 : out  std_logic;
          ccdD_02 : out  std_logic;
          ccdD_03 : out  std_logic;
          ccdD_04 : out  std_logic;
          ccdD_05 : out  std_logic;
          ccdD_06 : out  std_logic;
          ccdD_07 : out  std_logic;
          ccdD_08 : out  std_logic;
          ccdD_09 : out  std_logic;
          ccdD_10 : out  std_logic;
         ccdD_11 : out  std_logic;
          ccdD_12 : out  std_logic;
          ccdD_13 : out  std_logic;
          ccdD_14 : out  std_logic;
          ccdD_15 : out  std_logic;
          ccdD_16 : out  std_logic;
          ccdD_17 : out  std_logic;
          ccdD_18 : out  std_logic;
          ccdD_19 : out  std_logic;
          ccdD_20 : out  std_logic;
          ccdD_21 : out  std_logic;
          ccdD_22 : out  std_logic;
          ccdD_23 : out  std_logic;
          ccdD_24 : out  std_logic;
          ccdD_25 : out  std_logic;
          ccdD_26 : out  std_logic;
          ccdD_27 : out  std_logic;
          ccdD_28 : out  std_logic;
          ccdD_29 : out  std_logic;
          ccdD_30 : out  std_logic;
          ccdD_31 : in  std_logic;
          ccdD_32 : inout   std_logic;
          ccdD_33 : inout  std_logic;
          ccdD_34 : inout  std_logic;
          ccdD_35 : inout  std_logic;
          ccdD_36 : inout  std_logic;
          ccdD_37 : inout  std_logic;
          ccdD_38 : inout  std_logic;
          ccdD_39 : inout  std_logic;
          ccdD_40 : out    std_logic
],[
          ccdD_01 : inout   std_logic;
          ccdD_02 : out  std_logic;
          ccdD_03 : in   std_logic;
          ccdD_04 : in   std_logic;
          ccdD_05 : in   std_logic;
          ccdD_06 : out  std_logic;
          ccdD_07 : in   std_logic;
          ccdD_08 : in   std_logic;
          ccdD_09 : in   std_logic;
          ccdD_10 : in   std_logic;
          ccdD_11 : in   std_logic;
          ccdD_12 : in   std_logic;
          ccdD_13 : in   std_logic;
          ccdD_14 : in   std_logic;
          ccdD_15 : in   std_logic;
          ccdD_16 : out  std_logic;
          ccdD_17 : in   std_logic;
          ccdD_18 : in   std_logic;
          ccdD_19 : in   std_logic;
          ccdD_20 : in   std_logic;
          ccdD_21 : in   std_logic;
          ccdD_22 : in   std_logic;
          ccdD_23 : in   std_logic;
          ccdD_24 : in   std_logic;
          ccdD_25 : in   std_logic;
          ccdD_26 : in   std_logic;
          ccdD_27 : in   std_logic;
          ccdD_28 : in   std_logic;
          ccdD_29 : in   std_logic;
          ccdD_30 : in   std_logic;
          ccdD_31 : in   std_logic;
          ccdD_32 : in   std_logic;
          ccdD_33 : in   std_logic;
          ccdD_34 : in   std_logic;
          ccdD_35 : in   std_logic;
          ccdD_36 : in   std_logic;
          ccdD_37 : in   std_logic;
          ccdD_38 : in   std_logic;
          ccdD_39 : in   std_logic;
          ccdD_40 : in   std_logic
])
);
end c2a;

architecture structural of c2a is

component FD is
port (D : in std_logic;
C : in std_logic;
Q : out std_logic);
end component; 

signal clock: std_logic;

signal hostCLK: std_logic;

type hostState_type is ( RESET, INSN, INSN_SHIFT, DATA, DATA_SHIFT );
signal hostReset : std_logic;
signal hostState: hostState_type;
signal hostInsn : std_logic_vector(7 downto 0);
signal hostData : std_logic_vector(31 downto 0);

signal debugCounter : std_logic_vector(31 downto 0);
signal debugAddr : std_logic_vector(31 downto 0);
signal debugValue : std_logic_vector(31 downto 0);

type ramState_type is ( RESET, RAMWAIT, RAMREFRESH1, RAMREFRESH2, RAMRASPRECHARGE, RAMREAD1, RAMREAD2, RAMREAD3, RAMREAD4, RAMREAD5, RAMREAD6, RAMWRITE1, RAMWRITE2, RAMWRITE3, RAMWRITE4, RAMPROBE1, RAMPROBE2, RAMPROBE3, RAMPROBE4, RAMPROBE5, RAMPROBE6, RAMPUSH1, RAMPUSH2, RAMPUSH3, RAMPUSH4, RAMVDAC1, RAMVDAC2, RAMVDAC3, RAMVDAC4, RAMVDAC5, RAMVDAC6, RAMVDAC7  );
signal ramState : ramState_type;
signal ramStateDebug : std_logic_vector(7 downto 0);

signal ramStateDelay : std_logic_vector(3 downto 0);
signal ramRefreshAck, ramRefreshReq, ramRefreshPending : std_logic;
signal ramRefreshAddr : std_logic_vector(11 downto 0);
signal ramRefreshCounter : std_logic_vector(11 downto 0);

signal ramShouldPush : std_logic;

signal ramDir : std_logic;
signal ramDataIn, ramDataOut : std_logic_vector(31 downto 0);
signal ramDataWE : std_logic_vector(1 downto 0);
signal ramReadReq, ramReadAck, ramReadPending : std_logic;
signal ramWriteReq, ramWriteAck, ramWritePending : std_logic;
signal ramProbeReq, ramProbeAck, ramProbePending : std_logic;
signal ramVdacReq, ramVdacAck, ramVdacPending : std_logic;

signal mainFifoReadPtr : std_logic_vector(19 downto 0);
signal mainFifoWritePtr : std_logic_vector(19 downto 0);
signal mainFifoFullness : std_logic_vector(11 downto 0);
signal NmainFifoReadPtr : std_logic_vector(9 downto 0);

signal dummyCounter : std_logic_vector(7 downto 0);


type ccdState_type is (WAITING, LINETRANSFER0, LINETRANSFER, READPIXELS);
signal ccdState : ccdState_type;

signal ccdIAG, ccdSRG, ccdMark, ccdSAMPLE : std_logic;
signal ccdPixel, NccdPixel :std_logic_vector(11 downto 0);
signal ccdDelay : std_logic_vector(3 downto 0);
signal ccdLine : std_logic_vector(7 downto 0);

signal ccdDelayLine, NccdDelayLine : std_logic_vector(7 downto 0);
signal ccdADCDelay : std_logic_vector(3 downto 0);
signal ccdReadADC : std_logic;

signal ccdTestClk : std_logic;

signal frameIncr, frameIncrE, frameIncrNE, frameD, NframeD : std_logic_vector(29 downto 0);
signal frameLFSR, NframeLFSR : std_logic_vector(9 downto 0);
signal frameDsign : std_logic;
signal frameClock, frame0, frameInc : std_logic;
signal frameCounter : std_logic_vector(31 downto 0);

signal stepper : std_logic_vector(3 downto 0);
signal stepperPos, stepperInc : std_logic_vector(31 downto 0);
signal stepperClock : std_logic;
signal stepCount : std_logic_vector(15 downto 0);
signal stepCompare0 : std_logic_vector(7 downto 0);
signal stepCompare1 : std_logic_vector(7 downto 0);
signal stepCompare2 : std_logic_vector(7 downto 0);

signal i2cSCL, i2cSDA : std_logic;
signal i2cSDApull, i2cSDAin : std_logic;
signal silly : std_logic;

define(MEMORY_SIZE, 1024)
define(WORD_SIZE, 16)
define(PC_MODE, INC)

include(xpu_header.inc)

signal isabusADDRESS : std_logic_vector(19 downto 0);
signal isabusDATAIn, isabusDATA : std_logic_vector(7 downto 0);
signal isabusAEN, isabusIOCHRDY, isabusMEMWR, isabusMEMRD, isabusIOWR, isabusIORD, isabusRESET : std_logic;

signal isaDATAout : std_logic_vector(7 downto 0);
signal isaDATAdir : std_logic;

signal lm9627resetb, lm9627mclk : std_logic;
signal lm9627d : std_logic_vector(11 downto 0);
signal lm9627sample : std_logic_vector(15 downto 0);
signal lm9627pclk, lm9627hsync, lm9627vsync, lm9627sync : std_logic;

signal sampleD : std_logic_vector(11 downto 0);
signal sampleWritePtr, nsampleWritePtr : std_logic_vector(7 downto 0);
signal sampleScan : std_logic_vector(15 downto 0);

signal klatz: std_logic;

define(SIGNAL, [signal $1 : std_logic])
define(VECTOR, [signal $1 : std_logic_vector(eval($2 - 1) downto 0)])

VECTOR(windowWritePtr, 10);
VECTOR(windowReadPtr, 10);
SIGNAL(windowWrite);
VECTOR(windowScan,     4);
VECTOR(windowX,        10);
VECTOR(windowXtrue,    10);
VECTOR(windowY,        9);
VECTOR(NwindowX,       10);
VECTOR(NwindowY,       9);

VECTOR(pictureAddr, 8);
VECTOR(pictureData, 16);
VECTOR(pictureScan0, 8);
SIGNAL(pictureScan);
VECTOR(pictureState, 16);

-- ########################################################################
--                               NTSC OUT
-- ########################################################################

signal CLKIN_w, RESET_w, CLK0_dll, CLK0_g, CLK2X_dll, LOCKED_dll : std_logic;
signal CLK2X : std_logic;

signal ntscLinecount : std_logic_vector(8 downto 0);
signal ntscLinecountN : std_logic_vector(8 downto 0);
signal ntscHPixelcount : std_logic_vector(11 downto 0);
signal ntscHPixelcountN : std_logic_vector(11 downto 0);
signal ntscPixelcount : std_logic_vector(12 downto 0);
signal ntscPixelcountN : std_logic_vector(12 downto 0);
signal ntscSignal : std_logic;
VECTOR(ntscLevel, 2);
signal ntscEq, ntscSe, ntscBl, ntscAc : std_logic;
signal ntscInVdisp, ntscInH0, ntscInH1, ntscInH2, ntscInHdisp, ntscInV1 : std_logic;
signal ntscBitmap : std_logic_vector(0 downto 0);
signal ntsc300N, ntsc600N : std_logic;

signal ntscData : std_logic_vector(7 downto 0);

signal scanX : std_logic_vector(12 downto 0);
signal scanY : std_logic_vector(8 downto 0);
signal scanActive : std_logic;

signal dscanDigit : std_logic_vector(4 downto 0);
signal dscanXz : std_logic_vector(2 downto 0);
signal dscanYz : std_logic_vector(4 downto 0);
signal dscanNibble : std_logic_vector(3 downto 0);
signal dscanDrive : std_logic_vector(6 downto 0);
signal dscanOut : std_logic;

VECTOR(vdacReadPtr, 10);
VECTOR(vdacReadPtrN, 10);
VECTOR(vdacWritePtr, 9);
VECTOR(vdacWritePtrN, 9);

-- ########################################################################
--                            MESSING AROUND
-- ########################################################################

signal xtdivider : std_logic_vector(1 downto 0);
signal debug : std_logic_vector(31 downto 0);
signal lm9627_ticks : std_logic_vector(31 downto 0);

VECTOR(debugout, 32);

------------------------------------------------------------------------

------------------------------------------------------------------------

begin 


clkpad : IBUFG  port map (I=>clock_in, O=>CLKIN_w);

dll    : CLKDLL port map (CLKIN=>CLKIN_w,     CLKFB=>CLK0_g, RST=>hostReset,
                          CLK0=>CLK0_dll,   CLK90=>open, CLK180=>open, CLK270=>open,
                          CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED_dll);
clkg   : BUFG   port map (I=>CLK0_dll,   O=>CLK0_g);
clk2xg : BUFG   port map (I=>CLK2X_dll,  O=>CLK2X);

--gclkdeskew: BUFG port map (I => clock_in, O => clock);
clock <= CLK0_g;

-- gclk1: BUFG port map (I => hostCLK_g, O => hostCLK);
hostCLK <= hostCLK_g;

hostReset <= hostIn and hostSta;

-- ########################################################################
--                          MEMORY CONTROLLER
-- ########################################################################

process (hostReset, clock)
begin
  if (hostReset = '1') then
    ramRefreshCounter <= X"000";
    ramRefreshReq <= '0';
  elsif (clock'event and clock = '1') then
    if (ramRefreshCounter = X"4e2") then
      ramRefreshCounter <= X"000";
      ramRefreshReq <= '1';
    else
      ramRefreshCounter <= ramRefreshCounter + 1;
      ramRefreshReq <= '0';
    end if;
  end if;
end process;

process (clock, vdacReadPtr, vdacWritePtr)
begin
  if (ntscInV1 = '0') then
    ramVdacReq <= '0';
  elsif (clock'event and clock = '1') then
    if ((vdacReadPtr(9 downto 1) - vdacWritePtr) /= "000000000") then
      ramVdacReq <= '1';
    else
      ramVdacReq <= '0';
    end if;
  end if;
end process;

a: FDCPE port map (D =>    '1',
                           CE =>   '1',
                           C =>    ramReadReq,
                           PRE =>  '0',
                           CLR =>  ramReadAck,
                           Q =>    ramReadPending);

b: FDCPE port map (D =>    '1',
                           CE =>   '1',
                           C =>    ramWriteReq,
                           PRE =>  '0',
                           CLR =>  ramWriteAck,
                           Q =>    ramWritePending);

c: FDCPE port map (D =>    '1',
                           CE =>   '1',
                           C =>    ramRefreshReq,
                           PRE =>  '0',
                           CLR =>  ramRefreshAck,
                           Q =>    ramRefreshPending);

d: FDCPE port map (D =>    '1',
                           CE =>   '1',
                           C =>    ramProbeReq,
                           PRE =>  '0',
                           CLR =>  ramProbeAck,
                           Q =>    ramProbePending);

e: FDCPE port map (D =>    '1',
                           CE =>   '1',
                           C =>    ramVdacReq,
                           PRE =>  '0',
                           CLR =>  ramVdacAck,
                           Q =>    ramVdacPending);

process (ramDir, ramDQ, ramDataIn, ramDataOut, mainFifoReadPtr)
begin
  if (ramDir = '1') then
    ramDQ <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
    ramDataIn <= ramDQ;
  else
    ramDQ <= ramDataOut;
  end if;
end process;

NmainFifoReadPtr <= mainFifoReadPtr(19 downto 10) + 1;

process (ntscInV1, ramState)
begin
--  if (ntscInV1 = '0') then
--    vdacWritePtrN <= "000000000";
--  els
if (ramState = RAMVDAC6) then
    vdacWritePtrN <= vdacWritePtr + 1;
  else
    vdacWritePtrN <= vdacWritePtr;
  end if;
end process;

process
begin
  wait until clock'event and clock = '1';
  vdacWritePtr <= vdacWritePtrN;
end process;

process (hostReset, clock)
begin
  if (hostReset = '1') then
    ramState <= RESET;
    ramDir <= '1';

  elsif (clock'event and clock = '1') then
    case ramState is

    when RESET =>
      ramStateDebug <= X"01";
      mainFifoReadPtr <= X"00000";
      mainFifoWritePtr <= X"00000";
      mainFifoFullness <= X"000";
      ramState <= RAMWAIT;

    when RAMWAIT  =>
      ramStateDebug <= X"02";
      ramRAS <= "1111";
      ramCAS <= "1111";
      ramWE <= '1';
      ramDir <= '1';

      ramRefreshAck <= '0';
      ramReadAck <= '0';
      ramWriteAck <= '0';
      ramProbeAck <= '0';
      ramVdacAck <= '0';

      if (ramRefreshPending = '1') then
        ramState <= RAMREFRESH1;
      elsif (ramShouldPush = '1') then
        ramState <= RAMPUSH1;
      elsif (ramVdacPending = '1') then
        ramState <= RAMVDAC1;
--      elsif (ramWritePending = '1') then
--        ramState <= RAMWRITE1;
      end if;

    when RAMREFRESH1 =>
      ramStateDebug <= X"03";
      ramRefreshAck <= '1';
      ramA(9 downto 0) <= ramRefreshAddr(9 downto 0);
      ramState <= RAMREFRESH2;
      ramStateDelay <= X"0";

    when RAMREFRESH2 =>
      ramStateDebug <= X"04";
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      if (ramStateDelay = X"4") then
        ramRefreshAddr(9 downto 0) <= ramRefreshAddr(9 downto 0) + 1;
        ramState <= RAMRASPRECHARGE;
        ramStateDelay <= X"0";
      else
        ramStateDelay <= ramStateDelay + 1;
      end if;
      
    when RAMRASPRECHARGE =>
      ramStateDebug <= X"05";
      ramDataWE <= "00";
      ramRAS <= "1111";
      ramCAS <= "1111";
      ramDir <= '1';
      if (ramStateDelay = X"3") then
        ramState <= RAMWAIT;
      else
        ramStateDelay <= ramStateDelay + 1;
      end if;

    -- Copy a block from mainFifoReadPtr to daskFifoWritePtr
    when RAMREAD1 =>
      ramStateDebug <= X"06";
      mainFifoFullness <= mainFifoFullness - 1;
      ramA(9 downto 0) <= mainFifoReadPtr(19 downto 10);
      ramState <= RAMREAD2;
      ramReadAck <= '1';

    when RAMREAD2 =>
      ramStateDebug <= X"07";
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      ramState <= RAMREAD3;

    when RAMREAD3 =>
      ramStateDebug <= X"08";
      ramA(9 downto 0) <= mainFifoReadPtr(9 downto 0);
      ramState <= RAMREAD4;

    when RAMREAD4 =>
      ramStateDebug <= X"09";
      ramCAS <= "0000";
      ramState <= RAMREAD5;
      mainFifoReadPtr(9 downto 0) <= mainFifoReadPtr(9 downto 0) + 1;

    when RAMREAD5 =>
      ramStateDebug <= X"10";
      ramA(9 downto 0) <= mainFifoReadPtr(9 downto 0);
      ramCAS <= "1111";
      ramState <= RAMREAD6;
      ramDataWE <= "01";
      --ramDataWE <= "10";

    when RAMREAD6 =>
      ramStateDebug <= X"11";
      ramCAS <= "0000";
      ramDataWE <= "00";
      ramA(9 downto 0) <= mainFifoReadPtr(9 downto 0);

    when RAMVDAC1 =>
      ramA(9 downto 0) <= "0" & vdacWritePtr;
      ramState <= RAMVDAC2;
      ramVdacAck <= '1';

    when RAMVDAC2 =>
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      ramState <= RAMVDAC3;

    when RAMVDAC3 =>
      ramA(9 downto 0) <= "0000000000";
      ramState <= RAMVDAC4;

    when RAMVDAC4 =>
      ramCAS <= "0000";
      ramState <= RAMVDAC5;

    when RAMVDAC5 =>
      -- RamDataIn(15 downto 0);
      pictureData(7 downto 0) <= vdacWritePtr(8 downto 1);
      pictureData(15 downto 8) <= vdacWritePtr(8 downto 1);
      ramState <= RAMVDAC6;

    when RAMVDAC6 =>
      ramState <= RAMVDAC7;

    when RAMVDAC7 =>
      ramState <= RAMRASPRECHARGE;

ifelse([
    when RAMPROBE1 =>
      ramStateDebug <= X"12";
      ramA(9 downto 0) <= debugAddr(19 downto 10);
      ramState <= RAMPROBE2;
      ramProbeAck <= '1';

    when RAMPROBE2 =>
      ramStateDebug <= X"13";
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      ramState <= RAMPROBE3;

    when RAMPROBE3 =>
      ramStateDebug <= X"14";
      ramA(9 downto 0) <= debugAddr(9 downto 0);
      ramState <= RAMPROBE4;

    when RAMPROBE4 =>
      ramStateDebug <= X"15";
      ramCAS <= "0000";
      ramState <= RAMPROBE5;

    when RAMPROBE5 =>
      ramStateDebug <= X"16";
      ramState <= RAMPROBE6;

    when RAMPROBE6 =>
      ramStateDebug <= X"17";
      ramState <= RAMRASPRECHARGE;
])


ifelse([
    when RAMWRITE1 =>
      ramA(9 downto 0) <= debugAddr(19 downto 10);
      ramState <= RAMWRITE2;
      RamWriteAck <= '1';
      ramWE <= '0';
            
    when RAMWRITE2 =>
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      ramState <= RAMWRITE3;

    when RAMWRITE3 =>
      ramA(9 downto 0) <= debugAddr(9 downto 0);
      ramState <= RAMWRITE4;
      ramDataOut <= debugValue;
      ramDir <= '0';

    when RAMWRITE4 =>
      ramCAS <= "0000";
      ramState <= RAMRASPRECHARGE;
    ])

ifelse([
    -- Copy a block from dacFifoReadPtr to mainFifoWritePtr
    when RAMPUSH1 =>
      ramStateDebug <= X"18";
      mainFifoFullness <= mainFifoFullness + 1;
      ramA(9 downto 0) <= mainFifoWritePtr(19 downto 10);
      ramState <= RAMPUSH2;
      ramWE <= '0';
      ramDir <= '0';
            
    when RAMPUSH2 =>
      ramStateDebug <= X"19";
      ramRAS(0) <= '0';
      ramRAS(2) <= '0';
      ramState <= RAMPUSH3;

    when RAMPUSH3 =>
      ramStateDebug <= X"20";
      ramCAS <= "1111";
      ramA(9 downto 0) <= mainFifoWritePtr(9 downto 0);
      mainFifoWritePtr(7 downto 0) <= mainFifoWritePtr(7 downto 0) + 1;
      ramState <= RAMPUSH4;
      ramDataOut <= dacFifoReadData;
      dacFifoReadPtr <= NdacFifoReadPtr;

    when RAMPUSH4 =>
      ramStateDebug <= X"21";
      ramCAS <= "0000";
      if (mainFifoWritePtr(7 downto 0) /= X"00") then
        ramState <= RAMPUSH3;
      else
        mainFifoWritePtr(19 downto 8) <= mainFifoWritePtr(19 downto 8) + 1;
        ramState <= RAMRASPRECHARGE;
      end if;
])

    when others =>
      ramStateDebug <= X"22";
      ramState <= RAMWAIT;

    end case;

  end if;
end process;

debugout <= 
        "000" & vdacWritePtr &  -- 12 bits
        "00" & vdacReadPtr &    -- 12 bits
        "000000" & ramVdacPending & ramVdacReq;

-- ************************************************************************
--                          NTSC OUT
-- ************************************************************************

-- line is 63.5us.  at 40MHz
-- 2540 clocks

process (ntscLineCount, ntscPixelcount, ntscHPixelcount)
begin
  if (hostReset = '1') then
    ntscHPixelcountN <= "eval(0,2,12)";
    ntscPixelcountN <= "eval(0,2,13)";
    ntscLinecountN <= "eval(0,2,9)";
  else
    if (ntscHPixelcount = "eval(2542-1,2,12)") then
      ntscHPixelcountN <= "eval(0,2,12)";
    else
      ntscHPixelcountN <= ntscHPixelcount + 1;
    end if;

    -- 63.556 * 80 = 5084
    if (ntscPixelcount = "eval(5084-1,2,13)") then
      ntscPixelcountN <= "eval(0,2,13)";
      if (ntscLinecount = "100000111") then
        ntscLinecountN <= "000000000";
      else
        ntscLinecountN <= ntscLinecount + 1;
      end if;
    else
      ntscPixelCountN <= ntscPixelcount + 1;
      ntscLinecountN <= ntscLinecount;
    end if;
  end if;
end process;

process (ntscLineCount, ntscPixelcount, ntscHPixelcount)
begin
  -- Equalization
  if (ntscHPixelcount(11 downto 3) < "eval(23,2,9)") then
    ntscEq <= '0';
  else
    ntscEq <= '1';
  end if;

  -- Serration
  if (ntscHPixelcount(11 downto 3) < "eval((318 - 45),2,9)") then
    ntscSe <= '0';
  else
    ntscSe <= '1';
  end if;

  -- lines 0-8 are not ntscInVdisp
  if ("eval(8,2,9)" < ntscLinecount) then
    ntscInVdisp <= '1';
  else
    ntscInVdisp <= '0';
  end if;

  -- ntscSignal is only valid when (ntscLinecount <= 8)
  case ntscLinecount(3 downto 0) is
  when X"0" =>
      ntscSignal <= ntscEq;
  when X"1" =>
      ntscSignal <= ntscEq;
  when X"2" =>
      ntscSignal <= ntscEq;
  when X"3" =>
      ntscSignal <= ntscSe;
  when X"4" =>
      ntscSignal <= ntscSe;
  when X"5" =>
      ntscSignal <= ntscSe;
  when X"6" =>
      ntscSignal <= ntscEq;
  when X"7" =>
      ntscSignal <= ntscEq;
  when X"8" =>
      ntscSignal <= ntscEq;
  when others =>
      ntscSignal <= 'X';
  end case;

  if (ntscPixelcount(12 downto 3) < "eval(47,2,10)") then
    ntscInH0 <= '1';
  else
    ntscInH0 <= '0';
  end if;


define(NBORDER, 40)
define(SBORDER, 30)
define(WBORDER, 50)
define(EBORDER, 61)

-- these values give
--    width  400*8 clocks
--    height 193 lines

-- for 320x240 source, H every 10 pixels, V every 0.8 pixels

  if (ntscPixelcount(12 downto 3) < "eval(62 + 47 + WBORDER,2,10)") then
    ntscInH1 <= '1';
  else
    ntscInH1 <= '0';
  end if;

  if (ntscPixelcount(12 downto 3) < "eval(620 - EBORDER,2,10)") then
    ntscInH2 <= '1';
  else
    ntscInH2 <= '0';
  end if;

  if (("eval(NBORDER, 2, 9)" < ntscLinecount) AND
        (ntscLinecount < "eval(263 - SBORDER, 2, 9)")) then
    ntscInV1 <= '1';
  else
    ntscInV1 <= '0';
  end if;

  if (ntscInH0 = '1') then
    ntscLevel <= "00";          -- h sync: blacker than black
  elsif (ntscInH1 = '1') then
    ntscLevel <= "01";          -- back porch
  elsif (ntscInH2 = '1') and (ntscInV1 = '1') then
    ntscLevel <= pictureScan & "1";
  else
    ntscLevel <= "01";          -- front porch
  end if;

  ntscInHdisp <= NOT ntscInH0 AND NOT ntscInH1 AND ntscInH2;

  if (ntscInV1 = '0') then
    vdacReadPtrN <= "1000000000";
  elsif (((ntscInV1 AND ntscInHdisp) = '1') AND (ntscPixelCount(2 downto 0) = "111")) then
    vdacReadPtrN <= vdacReadPtr + 1;
  else
    vdacReadPtrN <= vdacReadPtr;
  end if;

  if (ntscInVdisp = '0') then
    ntsc300N <= ntscSignal;     -- first 9 lines
    ntsc600N <= ntscSignal;
  else
    ntsc300N <= ntscLevel(0);      -- rest of field
    ntsc600N <= ntscLevel(1);
  end if;

end process;

process (ntscPixelcount, ntscLinecount)
begin
  if ((ntscPixelcount(12 downto 8) < "00100") or 
      ("10010" < ntscPixelcount(12 downto 8))) then
    scanActive <= '0';
  else
    scanActive <= '1';
  end if;
  scanX <= ntscPixelcount - "eval(0x400,2,13)";
  scanY <= ntscLinecount;
end process;

process (scanX, scanY)
begin
  dscanDigit(3 downto 0) <= X"C" - scanX(11 downto 8);

  if (scanX(7 downto 0) < "eval(256 * 1 / 6, 2, 7)") then
    dscanXz <= "001";
  elsif (scanX(7 downto 0) < "eval(256 * 4 / 6, 2, 7)") then
    dscanXz <= "010";
  elsif (scanX(7 downto 0) < "eval(256 * 5 / 6, 2, 7)") then
    dscanXz <= "100";
  else
    dscanXz <= "000";
  end if;

  case scanY(4 downto 2) is
    when "000" => dscanYz <= "00001";
    when "001" => dscanYz <= "00010";
    when "010" => dscanYz <= "00010";
    when "011" => dscanYz <= "00100";
    when "100" => dscanYz <= "01000";
    when "101" => dscanYz <= "01000";
    when "110" => dscanYz <= "10000";
    when others => dscanYz <= "00000";
  end case;

  case dscanDigit(2 downto 0) is
    when "000" => dscanNibble <= debug(3 downto 0);
    when "001" => dscanNibble <= debug(7 downto 4);
    when "010" => dscanNibble <= debug(11 downto 8);
    when "011" => dscanNibble <= debug(15 downto 12);
    when "100" => dscanNibble <= debug(19 downto 16);
    when "101" => dscanNibble <= debug(23 downto 20);
    when "110" => dscanNibble <= debug(27 downto 24);
    when "111" => dscanNibble <= debug(31 downto 28);
    when others => null;
  end case;
   
--                              6543210
  case dscanNibble is
    when X"0" => dscanDrive <= "1110111";
    when X"1" => dscanDrive <= "0100100";
    when X"2" => dscanDrive <= "1011101";
    when X"3" => dscanDrive <= "1101101";
    when X"4" => dscanDrive <= "0101110";
    when X"5" => dscanDrive <= "1101011";
    when X"6" => dscanDrive <= "1111011";
    when X"7" => dscanDrive <= "0100101";
    when X"8" => dscanDrive <= "1111111";
    when X"9" => dscanDrive <= "1101111";
    when X"a" => dscanDrive <= "0111111";
    when X"b" => dscanDrive <= "1111010";
    when X"c" => dscanDrive <= "1011000";
    when X"d" => dscanDrive <= "1111100";
    when X"E" => dscanDrive <= "1011011";
    when X"F" => dscanDrive <= "0011011";
    when others => null;
  end case;

  dscanOut <= NOT dscanDigit(3) AND 
              ((dscanDrive(0) AND (dscanXz(0) OR dscanXz(1) OR dscanXz(2)) AND dscanYz(0)) OR
               (dscanDrive(1) AND dscanXz(0) AND (dscanYz(0) OR dscanYz(1) OR dscanYz(2))) OR
               (dscanDrive(2) AND dscanXz(2) AND (dscanYz(0) OR dscanYz(1) OR dscanYz(2))) OR
               (dscanDrive(3) AND (dscanXz(0) OR dscanXz(1) OR dscanXz(2)) AND dscanYz(2)) OR
               (dscanDrive(4) AND dscanXz(0) AND (dscanYz(2) OR dscanYz(3) OR dscanYz(4))) OR
               (dscanDrive(5) AND dscanXz(2) AND (dscanYz(2) OR dscanYz(3) OR dscanYz(4))) OR
               (dscanDrive(6) AND (dscanXz(0) OR dscanXz(1) OR dscanXz(2)) AND dscanYz(4)));

end process;

process
begin
  wait until CLK2X'event and CLK2X = '1';
  ntscHPixelcount <= ntscHPixelcountN;
  ntscPixelcount <= ntscPixelcountN;
  ntscLinecount <= ntscLinecountN;
  vdacReadPtr <= vdacReadPtrN;
  ntsc300 <= ntsc300N;
  ntsc600 <= ntsc600N;
  --debugout <= ntsc300N & ntsc600N & ntscInVdisp & ntscInHdisp & "000" & ntscLineCount & "000" & ntscPixelcount;
--  debugout <= "0000" & ntscHPixelcount & "000" & ntscPixelcount;
--  debugout <= "000" & ntscLinecount & "000" & ntscPixelcount & "00" & ntsc600N & ntsc300N;
 
end process;


-- ########################################################################
--                               FRAME TIMER
-- ########################################################################

process
begin
  wait until clock'event and clock = '1';
  frameD <= NframeD;
end process;

frameDsign <= frameD(29);

process (frameD, frameIncr)
begin
  if (frameDsign = '1') then
    frameIncr <= frameIncrE;
  else
    frameIncr <= frameIncrNE;
  end if;
  if (hostReset = '1') then
    NframeD <= "eval(0, 2, 30)";
  else
    NframeD <= frameD + frameIncr;
  end if;
end process;

process
begin
  wait until frameDsign'event and frameDsign = '1';
  frameLFSR <= NframeLFSR;
end process;

process (frameLFSR)
begin
  if (frameLFSR = "eval(0x2b2, 2, 10)") then
    NframeLFSR <= "eval(0, 2, 10)";
    frame0 <= '1';
  else
    NframeLFSR <= frameLFSR(8 downto 0) & NOT (frameLFSR(9) XOR frameLFSR(6));
    frame0 <= '0';
  end if;
end process;

frameInc <= frame0 AND frameDsign;
frameff: FD port map(D => frameInc, c => clock, Q => frameClock);

process
begin
  wait until frameClock'event and frameClock = '1';
  frameCounter <= frameCounter + 1;
end process;

-- ########################################################################
-- #                                 XPU
-- ########################################################################

include(xpu_behavioral.inc)
xpuRESET <= hostSTA;
--xpuCLOCKDRIVER: BUFG port map (I => clock, O => xpuCLOCK);
xpuCLOCK <= clock;

-- ########################################################################
-- #                               ISA BUS
-- ########################################################################


-- isaDATAdir 1 means input, 0 means output

isacb0: BUFE port map (I => isaDATAout(0), O => isabusDATA(0), E => NOT isaDATAdir);
isacb1: BUFE port map (I => isaDATAout(1), O => isabusDATA(1), E => NOT isaDATAdir);
isacb2: BUFE port map (I => isaDATAout(2), O => isabusDATA(2), E => NOT isaDATAdir);
isacb3: BUFE port map (I => isaDATAout(3), O => isabusDATA(3), E => NOT isaDATAdir);
isacb4: BUFE port map (I => isaDATAout(4), O => isabusDATA(4), E => NOT isaDATAdir);
isacb5: BUFE port map (I => isaDATAout(5), O => isabusDATA(5), E => NOT isaDATAdir);
isacb6: BUFE port map (I => isaDATAout(6), O => isabusDATA(6), E => NOT isaDATAdir);
isacb7: BUFE port map (I => isaDATAout(7), O => isabusDATA(7), E => NOT isaDATAdir);

isabusAEN <= '0';
-- old IO scheme
ifelse([
isaDATAdir <= cpuIOport2d(15);
isaDataOut <= cpuIOport2d(7 downto 0);
isabusADDRESS(4 downto 0) <= cpuIOport2a(4 downto 0);
isabusADDRESS(19 downto 5) <= "000000000011000";

isabusIORD <= cpuIOport4(0);
isabusIOWR <= cpuIOport4(1);
isabusMEMWR <= cpuIOport4(2);
isabusMEMRD <= cpuIOport4(3);

isabusRESET <= cpuIOport4(4);
])

--cpuIOread0 <= cpuST0(7 downto 0) & cpuST0(15 downto 8);
--cpuIOread2 <= "00000000" & isabusDATAIn;

ifelse([
cpuIOread3 <=
        "XXXXXXXXXXXXX" & 
        isabusIOCHRDY &
        hostIn &                -- 1    hostIn
        hostCLK_g;              -- 0    hostClk
])

isabusDATAIn(7) <= ccdD_39;
isabusDATAIn(6) <= ccdD_38;
isabusDATAIn(5) <= ccdD_37;
isabusDATAIn(4) <= ccdD_36;
isabusDATAIn(3) <= ccdD_35;
isabusDATAIn(2) <= ccdD_34;
isabusDATAIn(1) <= ccdD_33;
isabusDATAIn(0) <= ccdD_32;

ccdD_40 <= '0';          -- unused
ccdD_39 <= isabusDATA(7);
ccdD_38 <= isabusDATA(6);
ccdD_37 <= isabusDATA(5);
ccdD_36 <= isabusDATA(4);
ccdD_35 <= isabusDATA(3);
ccdD_34 <= isabusDATA(2);
ccdD_33 <= isabusDATA(1);
ccdD_32 <= isabusDATA(0);

isabusIOCHRDY <= ccdD_31;
ccdD_30 <= isabusAEN;

ccdD_29 <= isabusADDRESS(19);
ccdD_28 <= isabusADDRESS(18);
ccdD_27 <= isabusADDRESS(17);
ccdD_26 <= isabusADDRESS(16);
ccdD_25 <= isabusADDRESS(15);
ccdD_24 <= isabusADDRESS(14);
ccdD_23 <= isabusADDRESS(13);
ccdD_22 <= isabusADDRESS(12);
ccdD_21 <= isabusADDRESS(11);
ccdD_20 <= isabusADDRESS(10);
ccdD_19 <= isabusADDRESS(9);
ccdD_18 <= isabusADDRESS(8);
ccdD_17 <= isabusADDRESS(7);
ccdD_16 <= isabusADDRESS(6);
ccdD_15 <= isabusADDRESS(5);
ccdD_14 <= isabusADDRESS(4);
ccdD_13 <= isabusADDRESS(3);
ccdD_12 <= isabusADDRESS(2);
ccdD_11 <= isabusADDRESS(1);
ccdD_10 <= isabusADDRESS(0);

ccdD_06 <= isabusRESET;
ccdD_05 <= isabusRESET;

ccdD_04 <= isabusIORD;
ccdD_03 <= isabusIOWR;
ccdD_02 <= isabusMEMRD;
ccdD_01 <= isabusMEMWR;

ifelse([
ccdD_16 <= lm9627mclk;

ccdD_01 <= i2cSDA;
ccdD_02 <= i2cSCL;

ccdD_06 <= lm9627resetb;

i2cb: BUFE port map (I => '0', O => i2cSDA, E => i2cSDApull);
i2cp: PULLUP port map (O => i2cSDA);
i2cSDAin <= i2cSDA;

--xpuRESET <= cpuIOport4(6);
--xpuclockdriver: BUFG port map (I => cpuIOport4(5), O => xpuCLOCK);

--cpuIOread0 <= xpuSP & xpunSP & silly & "0000000";
--cpuIOread2 <= xpunST0(15 downto 0);

ifelse(A, A, [
process 
begin
  wait until clock'event and clock = '1';
  xtdivider <= xtdivider + 1;
end process;
lm9627mclk <= xtdivider(1);
],[
lm9627mclk <= xpuCLOCK;
])

lm9627d <= 
        ccdD_39 &
        ccdD_40 &
        ccdD_38 &
        ccdD_36 &
        ccdD_34 &
        ccdD_32 &
        ccdD_30 &
        ccdD_28 &
        ccdD_26 &
        ccdD_24 &
        ccdD_22 &
        ccdD_18;

lm9627hsync <=
        ccdD_10;
lm9627vsync <=
        ccdD_12;

-- gclk2: BUFG port map (I => ccdD_14, O => lm9627pclk);
-- lm9627pclk <= ccdD_14;

--zanzibar0: IBUF port map( I => ccdD_14, O => klatz);
--zanzibar1: BUFG port map( I => klatz, O => lm9627pclk);
lm9627pclk <= '0';
        
silly <= 
        ccdD_03 OR
        ccdD_04 OR
        ccdD_05 OR
        ccdD_07 OR
        ccdD_08 OR
        ccdD_09 OR
        ccdD_10 OR
        ccdD_11 OR
        ccdD_12 OR
        ccdD_13 OR
        ccdD_15 OR

        ccdD_17 OR
        ccdD_18 OR
        ccdD_19 OR
        ccdD_20 OR
        ccdD_21 OR
        ccdD_22 OR
        ccdD_23 OR
        ccdD_24 OR
        ccdD_25 OR
        ccdD_26 OR
        ccdD_27 OR
        ccdD_28 OR
        ccdD_29 OR
        ccdD_30 OR
        ccdD_31 OR
        ccdD_32 OR
        ccdD_33 OR
        ccdD_34 OR
        ccdD_35 OR
        ccdD_36 OR
        ccdD_37 OR
        ccdD_38 OR
        ccdD_39 OR
        ccdD_40;

lm9627sync <= lm9627hsync AND lm9627vsync;

lm9627sample <= X"0" & lm9627d;

samples: RAMB4_S16_S16
      port map (ADDRA => sampleWritePtr,
                DIA => lm9627sample,
      	        DOA => open,
                WEA => lm9627sync,
      	        CLKA => lm9627pclk,
      	        RSTA => hostReset,
                ENA => '1',
                ADDRB => scanX(11 downto 4),
                DIB => X"0000",
                DOB => sampleScan,
                WEB => '0',
      	        CLKB => clock,
      	        RSTB => hostReset,
                ENB => '1');

process (ntscPixelcount, pictureScan0)
begin
  if (pictureScan0(7 downto 4) < ntscPixelCount(3 downto 0)) then
    pictureScan <= '0';
  else
    pictureScan <= '1';
  end if;
end process;

pictureScan <= pictureScan0(0);

picture: RAMB4_S8_S16
dnl      generic map (include(excamera.inc))
      port map (ADDRA => vdacReadPtr(8 downto 0),
                DIA => X"00",
                DOA => pictureScan0,
                WEA => '0',
      	        CLKA => clock,
      	        RSTA => hostReset,
                ENA => '1',
                ADDRB => vdacWritePtr(7 downto 0),
                DIB => pictureData,
      	        DOB => open,
                WEB => '1',
      	        CLKB => clock,
      	        RSTB => hostReset,
                ENB => '1');


process (sampleWritePtr, lm9627vsync)
begin
 if (lm9627vsync = '0') then
   nsampleWritePtr <= X"00";
 elsif (nsampleWritePtr /= X"FF") then
   nsampleWritePtr <= sampleWritePtr + 1;
 else
   nsampleWritePtr <= X"FF";
 end if;
end process;

process
begin
  wait until lm9627pclk'event and lm9627pclk = '1';
--  if ((lm9627hsync = '1') AND (lm9627vsync = '1')) then
--    sampleD <= lm9627d;
--  end if;
  sampleWritePtr <= nsampleWritePtr;
end process;

window: RAMB4_S4_S4
      port map (ADDRA => windowWritePtr,
                DIA => lm9627d(11 downto 8),
      	        DOA => open,
                WEA => windowWrite,
      	        CLKA => lm9627pclk,
      	        RSTA => hostReset,
                ENA => '1',
                ADDRB => windowReadPtr,
                DIB => X"0",
                DOB => windowScan,
                WEB => '0',
      	        CLKB => clock,
      	        RSTB => hostReset,
                ENB => '1');

process (windowX, windowY)
begin
  if (windowX /= "eval(779, 2, 10)") then
    NwindowX <= windowX + 1;
    NwindowY <= windowY;
  else
    NwindowX <= binary(0, 10);
    NwindowY <= windowY + 1;
  end if;
end process;

process
begin
  wait until lm9627pclk'event and lm9627pclk = '1';
  if ((lm9627vsync = '0') and (windowY /= "eval(0, 2, 9)")) then
    windowX <= "eval(0, 2, 10)";
    windowY <= "eval(0, 2, 9)";
  else
    windowX <= NwindowX;
    windowY <= NwindowY;
  end if;
end process;

process (windowX, windowY)
begin
  windowXtrue <= windowX - debug(9 downto 0);
  if ((windowXtrue(9 downto 5) = "00000") and
      (windowY(8 downto 5) = "0000")) then
    windowWrite <= '1';
  else
    windowWrite <= '0';
  end if;
  windowWritePtr <= windowY(4 downto 0) & windowXtrue(4 downto 0);
end process;

windowReadPtr <= scanY(5 downto 1) & scanX(11 downto 7);

--debug <= "000000" & windowWritePtr & "000000" & windowReadPtr;

ifelse([
process
begin
  wait until lm9627pclk'event and lm9627pclk = '1';
  if (lm9627vsync = '0') then
    if (lm9627_ticks /= X"00000000") then
      debug(23 downto 0) <= lm9627_ticks(23 downto 0);
      debug(31 downto 24) <= debug(31 downto 24) + 1;
      lm9627_ticks <= X"00000000";
    end if;
  else
    lm9627_ticks <= lm9627_ticks + 1;
  end if;
end process;
])
])

process
begin
  wait until xpuCLOCK'event and xpuCLOCK = '1';
  if (xpuIOWrite = '1') then
    if (xpuIOAddr(8) = '1') then
      hostOUT <= xpuIODout(0);
      i2cSDApull <= xpuIODout(1);
      i2cSCL <= xpuIODout(2);
      lm9627resetb <= NOT xpuIODout(3);
    end if;
ifelse(VERSION, TCPIP, [
    if (xpuIOAddr(9) = '1') then
      isaDATAdir <= xpuIODout(8);
      isaDATAOut <= xpuIODout(7 downto 0);
    end if;
    if (xpuIOAddr(10) = '1') then
      isabusIORD <= xpuIODout(0);
      isabusIOWR <= xpuIODout(1);
      isabusMEMWR <= xpuIODout(2);
      isabusMEMRD <= xpuIODout(3);
      isabusRESET <= xpuIODout(4);
    end if;
    if (xpuIOAddr(11) = '1') then
      isabusADDRESS(4 downto 0) <= xpuIODout(4 downto 0);
    end if;
],[
    if (xpuIOAddr(10) = '1') then
      pictureAddr <= xpuIOAddr(7 downto 0);
    end if;
])
  end if;
end process;

ifelse(VERSION, TCPIP, [
isabusADDRESS(19 downto 5) <= "000000000011000";
])   

process (xpuIOAddr, silly, i2cSDAin, hostIn, hostCLK_g, lm9627d)
begin
  case (xpuIOAddr(1 downto 0)) is
    when "00" =>
      xpuIODin <=
--        "XXXXXXXXXXXXXXXX" & 
          "XXXXXXXXXXXX" & 
          silly &
          i2cSDAin &              -- 2    STA013 I2C SDA
          hostIn &                -- 1    hostIn
          hostCLK_g;              -- 0    hostClk
    when "01" =>
      --xpuIODin <= "0000000000000000000" & lm9627hsync & sampleD;
      xpuIODin <= X"00" & isabusDATAIn;
    when others =>
      xpuIODin <= X"include(ident)";
  end case;
end process;

silly <= 
        ccdD_31;

ccdD_07 <= '0';
ccdD_08 <= '0';
ccdD_09 <= '0';

end structural;

-- foo! bar!