define(HIBIT, eval(WORD_SIZE - 1))

signal xpuRESET : std_logic;
signal xpuCLOCK : std_logic;

signal xpuPC    : std_logic_vector(9 downto 0);
signal xpunPC   : std_logic_vector(9 downto 0);
signal xpuiPC   : std_logic_vector(9 downto 0);
signal xpunPCR  : std_logic_vector(9 downto 0);
signal xpuADDRA : std_logic_vector(9 downto 0);
signal xpuADDRB : std_logic_vector(9 downto 0);

signal xpuDINA : std_logic_vector(15 downto 0);
signal xpuDINB : std_logic_vector(HIBIT downto 0);
signal xpuDOUTA : std_logic_vector(15 downto 0);
signal xpuDOUTB : std_logic_vector(HIBIT downto 0);
signal xpuInsn : std_logic_vector(15 downto 0);

signal xpuST0 : std_logic_vector(HIBIT downto 0);
signal xpunST0 : std_logic_vector(HIBIT downto 0);
signal xpuST1 : std_logic_vector(HIBIT downto 0);

signal xpuWEB : std_logic;

signal xpuCSP : std_logic_vector(3 downto 0);
signal xpunCSP : std_logic_vector(3 downto 0);
signal xpuCSPd : std_logic_vector(1 downto 0);

signal xpuSP : std_logic_vector(3 downto 0);
signal xpunSP : std_logic_vector(3 downto 0);
signal xpuSPd : std_logic_vector(1 downto 0);

signal xpuDWE : std_logic;

signal xpuWEPC : std_logic;

signal xpuDECALU : std_logic;           -- decode: is current insn ALU op
signal xpuDECALUg : std_logic;           -- decode: is current insn ALU op
signal xpuDECIMM : std_logic;           -- decode: is current insn IMM op
signal xpuDECIMMg : std_logic;           -- decode: is current insn IMM op
signal xpuDECCALLg : std_logic;           -- decode: is current insn CALL op
signal xpuDECCALL : std_logic;           -- decode: is current insn CALL op
signal xpuDECWRITE : std_logic;         
signal xpuDECRETURN : std_logic;
signal xpuDECRETURNg : std_logic;
signal xpuDECALUOP : std_logic_vector(2 downto 0);
signal xpuDECLOGOP : std_logic_vector(3 downto 0);

-- ALU

ifelse(WORD_SIZE, 16, [
signal xpuSUM : std_logic_vector(32 downto 0);
])
ifelse(WORD_SIZE, 32, [
signal xpuSUM0 : std_logic_vector(32 downto 0);
signal xpuSUM1 : std_logic_vector(32 downto 0);
])
signal xpuADDERS : std_logic_vector(HIBIT downto 0);
signal xpuADDERC : std_logic;
signal xpuLOGIC : std_logic_vector(HIBIT downto 0);

signal xpuPRED0, xpuPRED : std_logic;

signal xpuIORead, xpuIOWrite : std_logic;
signal xpuIOAddr : std_logic_vector(HIBIT downto 0);
signal xpuIODout : std_logic_vector(HIBIT downto 0);
signal xpuIODin  : std_logic_vector(HIBIT downto 0);

component RAMB4_S16_S16
generic( INIT_00, INIT_01, INIT_02, INIT_03,
         INIT_04, INIT_05, INIT_06, INIT_07,
         INIT_08, INIT_09, INIT_0a, INIT_0b, 
         INIT_0c, INIT_0d, INIT_0e, INIT_0f :
 BIT_VECTOR(255 downto 0) :=
 X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF");
port (
ADDRA: IN std_logic_vector(7 downto 0);
DIA: IN std_logic_vector(15 downto 0);
WEA: IN std_logic;
CLKA: IN std_logic;
RSTA: IN std_logic;
ENA: IN std_logic;
DOA: OUT std_logic_vector(15 downto 0);
ADDRB: IN std_logic_vector(7 downto 0);
DIB: IN std_logic_vector(15 downto 0);
WEB: IN std_logic;
CLKB: IN std_logic;
RSTB: IN std_logic;
ENB: IN std_logic;
DOB: OUT std_logic_vector(15 downto 0)
);
END component;

component RAMB4_S1_S16
generic( INIT_00, INIT_01, INIT_02, INIT_03,
         INIT_04, INIT_05, INIT_06, INIT_07,
         INIT_08, INIT_09, INIT_0a, INIT_0b, 
         INIT_0c, INIT_0d, INIT_0e, INIT_0f :
 BIT_VECTOR(255 downto 0) :=
 X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF");
port (
ADDRA: IN std_logic_vector(11 downto 0);
DIA: IN std_logic_vector(0 downto 0);
WEA: IN std_logic;
CLKA: IN std_logic;
RSTA: IN std_logic;
ENA: IN std_logic;
DOA: OUT std_logic_vector(0 downto 0);
ADDRB: IN std_logic_vector(7 downto 0);
DIB: IN std_logic_vector(15 downto 0);
WEB: IN std_logic;
CLKB: IN std_logic;
RSTB: IN std_logic;
ENB: IN std_logic;
DOB: OUT std_logic_vector(15 downto 0)
);
END component;

component RAMB4_S4_S4
generic( INIT_00, INIT_01, INIT_02, INIT_03,
         INIT_04, INIT_05, INIT_06, INIT_07,
         INIT_08, INIT_09, INIT_0a, INIT_0b, 
         INIT_0c, INIT_0d, INIT_0e, INIT_0f :
 BIT_VECTOR(255 downto 0) :=
 X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF");
port (
ADDRA: IN std_logic_vector(9 downto 0);
DIA: IN std_logic_vector(3 downto 0);
WEA: IN std_logic;
CLKA: IN std_logic;
RSTA: IN std_logic;
ENA: IN std_logic;
DOA: OUT std_logic_vector(3 downto 0);
ADDRB: IN std_logic_vector(9 downto 0);
DIB: IN std_logic_vector(3 downto 0);
WEB: IN std_logic;
CLKB: IN std_logic;
RSTB: IN std_logic;
ENB: IN std_logic;
DOB: OUT std_logic_vector(3 downto 0)
);
END component;

component RAMB4_S4_S8
generic( INIT_00, INIT_01, INIT_02, INIT_03,
         INIT_04, INIT_05, INIT_06, INIT_07,
         INIT_08, INIT_09, INIT_0a, INIT_0b, 
         INIT_0c, INIT_0d, INIT_0e, INIT_0f :
 BIT_VECTOR(255 downto 0) :=
 X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF");
port (
ADDRA: IN std_logic_vector(9 downto 0);
DIA: IN std_logic_vector(3 downto 0);
WEA: IN std_logic;
CLKA: IN std_logic;
RSTA: IN std_logic;
ENA: IN std_logic;
DOA: OUT std_logic_vector(3 downto 0);
ADDRB: IN std_logic_vector(8 downto 0);
DIB: IN std_logic_vector(7 downto 0);
WEB: IN std_logic;
CLKB: IN std_logic;
RSTB: IN std_logic;
ENB: IN std_logic;
DOB: OUT std_logic_vector(7 downto 0)
);
END component;