Using the SRL16E to make a synchronous FIFO

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Xilinx Spartan and Virtex FPGAs offer a 16-bit shift register primitive, the SRL16E. Using the SRL16E makes designs much smaller and faster, as described in the Xilinx white paper.

To make a synchronous FIFO in Verilog:

module fifo ( clk, datain, wr, dataout, rd, fullness);
  parameter WIDTH = 1;

  input clk;
  input [WIDTH-1:0] datain;
  input wr;
  output [WIDTH-1:0] dataout;
  input rd;
  output reg [4:0] fullness;

  always @(posedge clk)
  begin
    fullness <= (fullness + wr - rd);
  end
  wire [3:0] readaddr = (fullness - 1);

  genvar i;

  generate
    for (i = 0; i < WIDTH; i=i+1) begin : srl16
      SRL16E fifo16(
        .CLK(clk),
        .CE(wr),
        .D(datain[i]),
        .A0(readaddr[0]),
        .A1(readaddr[1]),
        .A2(readaddr[2]),
        .A3(readaddr[3]),
        .Q(dataout[i]));
    end
  endgenerate

endmodule

This fifo is variable width, and 16 entries deep. To make a 32-bit wide fifo:

wire fwr;       // fifo write
wire fdr;       // fifo read
wire [31:0] fifo_in;
wire [31:0] fifo_out;
wire [4:0] fifo_fullness;

fifo #(32) myfifo(.clk(sys_clk),
  .wr(fwr), .datain(fifo_in),
  .rd(frd), .dataout(fifo_out),
  .fullness(fifo_fullness));

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