website statistics

Loading the XESS XSA-3S1000 from PythonΒΆ

The XESS XSA-3S1000 is a popular FPGA development board with a good selection of peripherals. By default it comes with a parallel cable, with drivers for Windows and Linux.

xess-python.tar.gz

This is a small Python program, and accompanying files, for loading a bit file into the board. It comes with a sample bit file xessdemo.bit that flashes the board LEDs. For example:

$ ./xsload xessdemo.bit
Talking to XSA Board OK!
bitfile xessdemo.bit loaded, 402936 bytes
DONE = 0
0 / 402936
10000 / 402936
20000 / 402936
30000 / 402936
40000 / 402936
50000 / 402936
60000 / 402936
70000 / 402936
80000 / 402936
90000 / 402936
100000 / 402936
110000 / 402936
120000 / 402936
130000 / 402936
140000 / 402936
150000 / 402936
160000 / 402936
170000 / 402936
180000 / 402936
190000 / 402936
200000 / 402936
210000 / 402936
220000 / 402936
230000 / 402936
240000 / 402936
250000 / 402936
260000 / 402936
270000 / 402936
280000 / 402936
290000 / 402936
300000 / 402936
310000 / 402936
320000 / 402936
330000 / 402936
340000 / 402936
350000 / 402936
360000 / 402936
370000 / 402936
380000 / 402936
390000 / 402936
400000 / 402936
DONE = 1

xsload works by accessing the parallel port directly, talking to the XESS CPLD, configuring it with the XESS fast downloader if necessary - this takes a few minutes. After that’s done, the actual FPGA download shown above takes about 20 seconds.

Note

You must set jumper J9 to XS in order for this downloader to work.

I have a FreeBSD system, and since FreeBSD parallel port access is so easy, that’s what the Python script currently uses, hence you will need to do:

$ sudo chmod a+rw /dev/ppi0

It should be a simple matter, however, to adapt it to Linux or Windows, probably using pyparallel. If you do this, please mail me patches! Thanks.

More VHDL, Verilog and FPGA notes.