We build our FPGA projects on Linux (Ubuntu) using Xilinx WebPack ISE 11.X.
It is fiddly getting a project set up, so here is a small tarball containing a minimal one.
After extracting it, the structure is:
xilinx-sample/synth:
Makefile # The main Makefile - adapt this to your needs
xessdemo.bmm # Block RAM layout, empty for this project
xessdemo.ucf # Pin assignments and clock constraints
xilinx.mk # Generic Xilinx Makefile
xilinx.opt # Generic Xilinx synthesis options
xilinx-sample/verilog:
xessdemo.v # Single Verilog file
Then:
$ cd sample/synth
$ make
a whole bunch of Xilinx messages will appear, and after about a minute you should see a file xessdemo.bit. This is the FPGA image.
By editing the Makefile you can specify the chip and package, as well as project names and Verilog source files:
project = xessdemo
vendor = xilinx
family = spartan3s
part = xc3s1000-4ft256
top_module = xessdemo
vfiles = ../verilog/xessdemo.v
include xilinx.mk
You should not need to modify xilinx.mk or xilinx.opt.