VHDL, Verilog and FPGA notesΒΆ

These are some notes and projects on working with FPGAs.

Getting Started
Summary of FPGA development boards

A roundup of current entry-level FPGA boards, updated March 2011.

Loading the XESS XuLA from Python

A pure Python loader for the new XESS XuLA FPGA board. No drivers required.

The J1 Forth CPU

J1 is a minimal 16-bit stack-based CPU that can run Forth at 100 MIPS. Designed for FPGAs and coded in under 200 lines of Verilog, it uses block RAM for code and data, has large internal stacks, and executes one instruction per cycle without pipelining.

Generating NTSC composite video with an FPGA and two resistors

With the speed of an FPGA, all you need is two digital logic lines - and a page of VHDL - to generate NTSC composite video. This implementation uses PWM to get 16 shades of gray.

Simple transmit-only UART in Verilog

Short transmit-only UART; useful for adding an RS-232 debug port to your next design.

Homebrew CPU in an FPGA

A tiny stack-based 16-bit CPU from 2003.

Loading the XESS XSA-3S1000 from Python

Python loader for the popular XESS XSA-3S1000 development board.

RAM64X1S as a sine wave ROM

The Xilinx RAM64X1S primitive also makes an incredibly efficient ROM - in this case to make a 64-entry sine wave.

Using the SRL16E to make a synchronous FIFO

You can make an incredibly compact FIFO from Xilinx SRL16E primitives.

Signed comparison in Verilog

Signed operations and values have been part of Verilog for about a decade. This article explains a few common uses of signed values, and shows how to mix operations involving signed and unsigned values.

Making an arbitrary frequency clock in VHDL and Verilog

Notes on how to derive a fractional lower frequency clock in VHDL and Verilog.

Minimal Makefile for Xilinx WebPack

A minimal Makefile for building Xilinx WebPack ISE projects on Linux/Unix.


fpga4fun - FPGA projects and tutorials

John’s FPGA Page - VHDL and FPGA resources, many CPU projects

Mail: jamesb-2011@excamera.com