Loading the XESS XuLA from PythonΒΆ


The new XESS XuLA 50 and 200 are tiny low-cost FPGA boards.

They come with a full set of development tools, but I wanted to experiment directly with the JTAG interface.

Here is the first step: a JTAG bitstream downloader that reads a Xilinx .bit file and loads it into the FPGA using JTAG via the XuLA’s USB connection.


It loads the XuLA 200 in about half a second:

$ sudo python loader.py wumpus/firmware/j1_program.bit
xulaload, see http://excamera.com/sphinx/fpga-xula-python.html for details
Found XuLA on USB bus
  Product ID: 00 02
  Version: 1 0
  Description: XuLA
OK, found DEVICEID for XC3S200A
bitfile wumpus/firmware/j1_program.bit loaded, 149516 bytes
took 0.519022941589
load complete, USERCODE= 0xdecafbadL

Apart from Python and python-usb, there are no dependencies and no drivers to install.

The code is split up in a way that separates the USB, JTAG, Xilinx and XuLA specific parts. The next step is to use the same functions to drive the FPGA’s JTAG controller.

More VHDL, Verilog and FPGA notes.